1. Field of the Invention
The present invention relates to an electrode structure in a semiconductor device in which semiconductor chips are flip-chip-mounted, and a semiconductor wafer, a semiconductor device and an electronic device relating thereto.
2. Description of the Related Art
As an information communication device and an office-use electronic device are increasingly downsized and highly-functional in recent years, it is requested that an area reduction be realized and the number of external terminals for input/output be increased in a semiconductor device (semiconductor integrated circuit device or the like) which is installed in these devices. However, in the structure of a semiconductor device in which an electrode pad is formed in a periphery of a semiconductor chip and connected to an external circuit by means of a wire-bonding method, it is becoming difficult to have a compatibility between an increase in the number of external terminals and the downsizing of a semiconductor chip.
As the conventional technology for realizing these contradictory demands at the same time, such structures that are called the pad-on element structure and the flip-chip structure are increasingly often adopted. In the pad-on element structure, an electrode pad connected to outside by means of wire bonding or inner-lead bonding is formed on an active area. In the flip-chip structure, external connection terminals called bumps are formed on the electrode pad formed on the active area, and the external connection terminals are connected to an external circuit via the bumps.
FIG. 5 is a sectional view illustrating an electrode structure in a conventional semiconductor device of the BGA (Ball Grid Array) type. FIG. 6 is a sectional view illustrating a state where a semiconductor chip 1 shown in FIG. 5 is flip-chip-mounted on a wiring substrate 7, and under-fill resin 8 is then injected into between the semiconductor chip 1 and the wiring substrate 7. As shown in FIG. 5, an electrode pad 2 electrically connected to a semiconductor element and an insulation film 3 having an opening above the electrode pad 2 are formed on the semiconductor chip 1, and a ground metallic layer 5 is formed on an area above the electrode 2, the area including an upper portion and the opening of the insulation film 3. On the ground metallic layer 5, a metallic bump 6 made of solder is provided. As shown in FIG. 6, the semiconductor chip 1 is mounted on the wiring substrate 7 in a face-down manner, and the electrode pads 2 of the semiconductor chip 1 and electrode lands 7a of the wiring substrate 7 are mechanically and electrically connected to each other via the metallic bumps 6. The under-fill resin 8 is filled into between the metallic bumps 6 in a gap between the semiconductor chip 1 and the wiring substrate 7. The wiring substrate 7 is provided with solder balls 10 on a surface thereof opposite to a surface where the metallic bumps are formed.
The under-fill resin 8 is filled thereinto based on the following reason. In the case where the semiconductor device is subjected to the thermal history or the like, stress is applied to joining areas, more specifically, chip-side root portions of the metallic bumps 6 because a thermal expansion coefficient is different between the semiconductor chip 1 and the wiring substrate 7. In order to lessen the concentration of the stress, the under-fill resin 8 is injected into between the semiconductor chip 1 and the wiring substrate 7 to seal the gap. Thus constituted, the under-fill resin 8 is cured so that a bonding strength between the semiconductor chip 1 and the wiring substrate 7 is increased. In the under-fill resin 8, filler 9 having an appropriate size is added to resin 8a, which is a base material such as epoxy-based resin, in order for the under-fill resin 8 to obtain a thermal expansion coefficient similar to that of the semiconductor chip 1. When an amount and particle diameters of the filler 9 are adjusted, the thermal expansion coefficient is adjusted. The under-fill resin 8 also serves to prevent moisture from entering from outside and thereby improve the resistance to moisture.
Referring to process sectional views illustrated in FIGS. 7A and 7D, a semiconductor device manufacturing method according to the before-mentioned flip-chip mounting structure is described. As shown in FIG. 7A, a semiconductor chip 1 which has metallic bumps 6 formed on an electrode pad 2 by means of the electroplating method, printing method or the like, and a wiring substrate 7 on which metallic pads 7a are formed at positions corresponding to the metallic bumps 6 are prepared. Then, the semiconductor chip 1 is flip-chip-mounted on the wiring substrate 7.
As shown in FIG. 7B, when the metallic bumps 6 of the semiconductor chip 1 are reflowed, the solder is melted and the metallic bumps 6 and the metallic pads 7a are connected to each other. After that, as shown in FIG. 7C, a gap between the semiconductor chip 1 and the wiring substrate 7 is washed, and under-fill resin 8 is injected into the gap with a dispenser 11. The under-fill resin 8 is injected from a periphery of the chip, and capillarity makes the under-fill resin 8 spread onto an entire bottom surface of the semiconductor chip 1. As a result, the gap between the semiconductor chip 1 and the wiring substrate 7 is filled with the under-fill resin 8.
After that, a heat treatment is performed so that the under-fill resin 8 is cured, and the gap is thereby sealed. Then, as shown in FIG. 7D, the solder balls 10 are provided on the metallic pad drawn to a substrate surface opposite to a surface provided with the chip, and the solder balls 10 are reflowed. As a result of these steps, the semiconductor device of the BGA type is completed.
As the semiconductor is increasingly smaller and highly-functional in recent years, however, pitches of the metallic bumps 6 become smaller, and the gap between the semiconductor chip 1 and the wiring substrate 7 becomes narrower. When the gap is smaller, the root portions of the metallic bumps 6 are subjected to more stress. As a result, a crack 12 (see the bold line) extending from the root portion of the metallic bump 6 into the semiconductor chip 1 is more likely to occur. The fact that the crack 12 is more likely to occur when the gap is smaller is based on the following reason. Because the ground metallic layer 5 is formed on an area above the electrode pad 2, the area including the upper portion and the opening of the insulation film 3, the insulation film 3 is present, but the electrode pad 2 is not present immediately below and portions of the ground metallic layer 5. Accordingly, a mechanical strength at an area immediately below the end portions of the ground metallic layer 5 is lower than that at any other areas. Therefore, the crack 12 (see the bold line) is likely to occur from the area immediately below the end portions of the ground metallic layer 5, at which the mechanical strength is lower than at any other areas and develop into the semiconductor chip 1 when a large stress is applied to the root portion of the metallic bump 6.
As a constitution provided for controlling the generation of the crack 12 can be mentioned a conventional example 1 recited in the Japanese Patent Document (H04-196392 of the Japanese Patent Applications Laid-Open). The conventional example 1 is described referring to FIGS. 9A-9B. In the conventional example 1, a second insulation film 4 having a relatively large film thickness is formed on a first insulation film 3, and a ground metallic layer 5 having an uneven shape is formed between the second insulation film 4 and an electrode pad 2. The formation of the second insulation film 4 serves to reduce the crack in an interface of the ground metallic layer 5 starting from the end portions thereof. However, the crack 12 resulting from the concentration of the stress in the end portions of the ground metallic layer 5 still cannot be controlled effectively enough. Further, peeling 13 (see the bold line) is likely to occur because a bonding strength between the ground metallic layer 5 and the insulation film 4 is inadequate and a mechanical strength of the bump root portion is insufficient since the position of the end portions of the ground metallic layer 5 is higher than that of a central portion thereof. Further, this constitution is also characterized in that the electrode pad 2 is not present immediately below the end portions of the ground metallic layer 5.
As another constitution provided for controlling the generation of the crack 12 can be mentioned a conventional example 2 recited in the Japanese Patent Document (H2004-19550 of the Japanese Patent Applications Laid-Open). The conventional example 2 is described referring to FIG. 10. In the conventional example 2, openings of a first insulation film 3 and a second insulation film 4 have a slope shape, which serves to reduce the peeling starting from the end portions of the ground metallic layer 5. However, in the conventional example 2, wherein the end portions of the ground metallic layer 5 still extend upon the first insulation film 3, a bonding strength between the ground metallic layer 5 and the first insulation film 3 is inadequate, and the peeling cannot be completely controlled. Further, a gap between the root portion of the metallic bump 6 and the second insulation film 4 is reduced to the minimum, which may have such structural disadvantages as described below, significantly affecting the reliability of the semiconductor device:                the gap cannot be filled with the under-fill resin; and        the gap cannot be filled with filler contained in the under-fill resin.        
The conventional examples 1 and 2 include the following disadvantage in addition to the inconveniences mentioned earlier. As a semiconductor manufacturing process has been remarkably advanced in recent years, the structure of the semiconductor chip is increasingly miniaturized and highly-integrated. As a result, a copper wiring having a relatively small resistance is often used as a wiring material, and a material having a low dielectric constant (low-k) is also often used as an inter-layer insulation film. However, the material having a low dielectric constant is inferior in mechanical strength. When these materials are used in the conventional examples 1 and 2, therefore, the crack and the peeling are more likely to occur in any film having a low dielectric constant used in the semiconductor device on which the semiconductor chips have been mounted.